Tesla · Hardware · 6 Nov 2026
Tesla's chip slide renames HW4 to SI4 and sketches SI6 at 80x the compute, with Dojo 3 aimed at space
Tom's Hardware published a photographed Tesla slide on Friday that maps the company's next inference and training chips under a new "SI" label for Super Intelligence. The slide calls today's Full Self-Driving hardware SI4, lists SI5 at 40 times that baseline and SI6 at 80 times, and describes Dojo 3 as a chiplet design with stacked HBM optimized for space, training and scaling. Tesla and Elon Musk have not posted the slide themselves (as of 6 Nov 2026).
On this page
Updated
The editor holds Tesla and SpaceX shares. Supercharged Daily is independent and not affiliated with either company. Nothing here is financial advice.
Tesla unveils AI accelerator roadmap, adopts new 'SI' branding in 'Super Intelligence' push — SI6 to bring 80X more compute performance, Dojo 3 headed to space
— Tom's Hardware (@tomshardware) November 6, 2026
What the slide shows, as photographed
Tom's Hardware, in a piece by Anton Shilov published on 6 Nov, ran a photograph of a Tesla presentation slide about the chips powering its products, with image credit to Tesla. The outlet's X post went up at 7:04am ET Friday (4:04am PT). As of that publication, neither Tesla's official account nor Musk had shared the same graphic, so the public path into the document is Tom's Hardware's report and photo.
On the visible roadmap, inference chips are labeled SI4, SI5 and SI6. The training line shows D3 (Dojo 3). The SI prefix matches Tesla's move toward "Super Intelligence" naming. That branding has already shown up elsewhere in the Musk stack: on 4 Oct, Musk replied "Yes, we will make that change" when asked whether SpaceXAI would become SpaceXSI, after posting "No more AI / SI / It's better."
Yes, we will make that change
— Elon Musk (@elonmusk) October 4, 2026
SI4, SI5 and SI6: the multipliers on the slide
SI4 is described as "the current benchmark for Full Self-Driving," Tom's Hardware reports. That is HW4 under a new label: the same generation of vehicle computer Tesla has been shipping in current cars (also previously referred to as AI4). The SI4 name is a rebadge of chips already on the road, not a new part number for owners to wait on.
Process node for SI4 is the one place Tom's Hardware flags a conflict. The photographed slide allegedly lists 5nm, while the outlet says the production part is Samsung 7nm-class. Without a Tesla primary confirmation of either figure, both claims remain contested reporting.
SI5, still a development claim on the slide, is listed at a 40x improvement versus SI4. Tom's Hardware reports that gain as an 8x compute increase times a 5x silicon-optimization factor, with memory listed at 6x SI4, multi-chip module (MCM) packaging, and 3nm / 2nm node options.
SI6 is listed at an 80x improvement versus SI4, with MCM packaging and a 2nm node. Prefer the slide's memory figure of 8x more memory: Tom's Hardware's surrounding prose also described memory as about 9x over HW4, which is the outlet's reading, not a number to treat as absolute fact here.
Read those multipliers as relative claims against SI4, not as absolute TOPS or watt ratings. Absolute TOPS or PFLOPS ranges circulating around this story are Tom's Hardware estimates built on older HW3/HW4 commentary, and they are not used here. Calendar timing for SI6 from that prose is likewise omitted.
Dojo 3 leaves the wafer-scale SRAM path
D3 is labeled for training and described as "optimized for space, training, and scaling," according to Tom's Hardware's reading of the slide. Architecture notes point to a chiplet module, 2.5D plus 3D packaging, and stacked HBM. The manufacturing node is listed as TBA.
That is a break from Dojo D1's wafer-scale approach, which tied many D1 dies together with large on-wafer SRAM pools. Moving to chiplets and stacked HBM trades that SRAM-centric style for a more conventional high-bandwidth memory stack and modular packaging. Tom's Hardware notes the same architectural turn and ties the "space" wording to possible extraterrestrial deployment. The slide itself does not spell out radiation hardening, launch cadence or a ship date.
Status language matters. SI4 is the production benchmark already in vehicles. SI5, SI6 and D3 appear as roadmap and development entries on a presentation graphic. They are design targets until Tesla ships silicon or publishes a primary datasheet.
What is confirmed, and what is still only on the photo
Confirmed through Tom's Hardware's 6 Nov publication: a Tesla-credited slide using SI branding for inference chips, relative compute and memory multipliers for SI5 and SI6 versus SI4, MCM notes for those future inference parts, and a D3 training entry that calls out chiplets, 2.5D/3D packaging, stacked HBM, and optimization for space, training and scaling. Confirmed separately through Musk's 4 Oct posts: willingness to swap "AI" labels for "SI," including the SpaceXAI to SpaceXSI rename.
Not confirmed by a Tesla or Musk post of this slide, and not treated as fact here: absolute TOPS or PFLOPS for SI5 or SI6, a calendar year for SI6 production, and any third-party chart that compares those chips to Nvidia silicon. The useful owner takeaway today is narrower. Cars already running HW4 are on the SI4 baseline this roadmap uses. Everything past that line is still a slide, photographed by a trade outlet, waiting on primary Tesla publication and shipping hardware.
Sources: Anton Shilov / Tom's Hardware (6 Nov 2026); Tom's Hardware on X; Elon Musk on SI branding (4 Oct 2026); Elon Musk SpaceXSI rename reply. Hero photo: Steve Jurvetson / Wikimedia Commons, CC BY 2.0. Slide image credit in source article: Tesla, via Tom's Hardware. As of 6 Nov 2026.
— Alex R
